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Preliminary Datasheet
FEATURES
Broadband RF port: LF to 500 MHz Conversion gain: 3 dB Noise figure: 12 dB Input IP3: 24 dBm Input P1dB: 8.5 dBm LO drive: 0 dBm External control of mixer bias for low power operation Single-ended, 50 LO input ports High Input Impedance RF port Single-supply operation: 5 V @ 97 mA Power-down mode Exposed paddle LFCSP: 3 mm x 3 mm
Active Receive Mixer DC to 500 MHz AD8342
FUNCTIONAL BLOCK DIAGRAM
VPDC PWDN EXRB 12 11 BIAS 10 COMM 9
COMM 13
8
COMM
RFCM 14
7
IFOP
RFIN 15
6
IFOM
APPLICATIONS
Cellular base station receivers and transmitters ISM receivers and transmitters Radio links RF Instrumentation
VPMX 16
5
COMM
1
2
3 LOIN
4 COMM
VPLO LOCM
Figure 1.
GENERAL DESCRIPTION
The AD8342 is a high performance, broadband active mixer. It is well suited for demanding receive applications that require wide bandwidth on all ports and very low intermodulation distortion and noise figure. The AD8342 provides a typical conversion gain of 3dB at 500 MHz. The integrated LO driver supports a 50 input impedance with a low LO drive level, helping to minimize external component count. The high input impedance RF port can be terminated and driven single ended or a matching network can be used for best noise or power match. The RF input accepts input signals as large as 1.7 V p-p or 8 dBm (re: 50 ) at P1dB.
The open-collector differential outputs provide excellent balance and can be used with a differential filter or IF amplifier, such as the AD8369 or AD8351. These outputs may also be converted to a single-ended signal through the use of a matching network or a transformer (balun). When centered on the VPOS supply voltage, each of the differential outputs may swing 2.5 V p-p. The AD8342 is fabricated on an Analog Devices proprietary, high performance SiGe IC process. The AD8342 is available in a 16-lead LFCSP package. It operates over a -40C to +85C temperature range. An evaluation board is also available.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD8342 SPECIFICATIONS
Preliminary Datasheet
VS = 5 V, TA = 25C, fRF = 500 MHz, fLO = 600 MHz, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, unless otherwise noted. Table 1.
Parameter RF INPUT INTERFACE Return Loss DC Bias Level OUTPUT INTERFACE Output Impedance DC Bias Voltage Power Range LO INTERFACE LO Power Return Loss DC Bias Voltage POWER-DOWN INTERFACE PWDN Threshold PWDN Response Time PWDN Input Bias Current POWER SUPPLY Positive Supply Voltage Quiescent Current VPDC VPMX, IFOP, IFOM VPLO Total Quiescent Current Power-Down Current Conditions (Pin 15, RFIN and Pin 14, RFCM) Hi-Z input terminated off-chip Internally generated; port must be ac-coupled Differential impedance, f = 200 MHz Externally generated Via a 4:1 balun Min Typ 10 2.5 9||1 VS Max Unit dB V k||pF V dBm dBm dB V V s s A A 5.25 V mA mA mA mA A
4.75
5.25 +13 +4
-10 Internally generated; port must be ac-coupled
0 10 VS - 1.6 VS - 1.4 0.4 0.01 -80 +100
Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled 4.75 Supply current for bias cells Supply current for mixer, RBIAS = 1.82 k Supply current for LO limiting amplifier VS = 5 V Device disabled
5 5 57 35 97 500
TBD
TBD
Rev. PrB | Page 2 of 8
Preliminary Datasheet AC PERFORMANCE
VS = 5 V, TA = 25C, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, unless otherwise noted. Table 2.
Parameter RF Frequency Range LO Frequency Range IF Frequency Range Conversion Gain SSB Noise Figure Input Third-Order Intercept Conditions High Side LO Note: the upper "IF" is when used as an upconverter fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz fRF1 = 460 MHz, fRF2 = 461 MHz, fLO = 550 MHz, fIF = 90 MHz, each RF tone -10 dBm fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286MHz, fIF = 45MHz, each RF tone -10 dBm fRF1 = 460 MHz, fRF2 = 480 MHz, fLO = 550 MHz, fIF = 90 MHz fRF1 = 238 MHz, fRF2 = 248 MHz, fLO = 286 MHz, fIF = 48 MHz fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz LO Power = 0 dBm, fRF = 500 MHz, fLO = 600 MHz LO Power = 0 dBm, fRF = 500 MHz, fLO = 600 MHz LO Power = 0 dBm, fRF = 500 MHz, fLO = 600 MHz RF Power = -10 dBm, fRF = 500 MHz, fLO = 600 MHz RF Power = -10 dBm, fRF = 500 MHz, fLO = 600 MHz Min LF LF DC Typ
AD8342
Max 500 850 350
3.2 3.4 12.5 12.2 22.5 23.5 48 48 8.5 8.5 TBD TBD TBD TBD TBD
Unit MHz MHz MHz dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
Input Second-Order Intercept Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage 2xLO to IF Output Leakage RF to IF Output Leakage IF/2 Spurious
Rev. PrB | Page 3 of 8
AD8342 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage, VS RF Input Level LO Input Level PWDN Pin IFOP, IFOM Bias Voltage Minimum Resistor from EXRB to COMM Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V 12 dBm 12 dBm VS + 0.5 V 5.5 V 1.82 k 580 mW 77C/W 125C -40C to +85C -65C to +150C 300C
Preliminary Datasheet
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 4 of 8
Preliminary Datasheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMM PWDN VPDC EXRB
AD8342
12
11
10
9 8 7 6 5
COMM 13 RFCM 14 RFIN 15 VPMX 16
1 2 3 4
COMM IFOP IFOM COMM
04826-0-002
VPLO
LOCM
LOIN
Figure 2. 16-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4, 5, 8, 9, 13 6, 7 10 11 12 14 15 16 Mnemonic VPLO LOCM LOIN COMM IFOM, IFOP EXRB PWDN VPDC RFCM RFIN VPMX Function Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V. AC Ground for Limiting LO Amplifier, AC-Coupled to Ground. LO Input. Nominal input level 0 dBm, input level range -10 dBm to +4 dBm, re: 50 , ac-coupled. Device Common (DC Ground). Differential IF Outputs; Open Collectors, Each Requires DC Bias of 5.00 V (Nominal). Mixer Bias Voltage, Connect Resistor from EXRB to Ground, Typical Value of 1.82 k Sets Mixer Current to Nominal Value. Minimum resistor value from EXRB to ground = 1.82 k. Connect to Ground for Normal Operation. Connect pin to VS for disable mode. Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V. AC Ground for RF Input, AC-Coupled to Ground. RF Input. Must be ac-coupled. Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V.
Rev. PrB | Page 5 of 8
COMM
AD8342
5 4.5 4 C o n v e r s io n G a in - d B 3.5 3 2.5 2 1.5 1 0.5 0 100
Preliminary Datasheet
15 14 13 12 11
NF - dB
150 200 250 300 RF Frequency - MHz
10MHz
48MHz
90MHz
140MHz
10 9 8 7 6 5 100
350
400
450
500
150
200
250
300 RF Frequency - MHz
350
400
450
500
10MHz
48MHz
90MHz
140MHz
Figure 3. Conversion Gain vs. RF Frequency for Multiple IF Frequencies
Figure 4. Single Sideband Noise Figure vs RF Frequency for Multiple IF Frequencies
12 11
30
25
10
20
In p u t P 1 d B - d B m
9 8 7
IIP 3 - d B m
15
10
5
6 5 100
0 100
150
200
250
300 RF Frequency - MHz
350
400
450
500
150
200
250
300 RF Frequency - MHz
350
400
450
500
10MHz
48MHz
90MHz
140MHz
10MHz
48MHz
90MHz
140MHz
Figure 6.. Input IP3 vs. RF Frequency for Multiple IF Frequencies
Figure 5. Input Compression Point vs RF Frequency for Multiple IF Frequencies
Rev. PrB | Page 6 of 8
Preliminary Datasheet EVALUATION BOARD
AD8342
An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a balun transformer. The schematic for the evaluation board is presented in Figure 7.
Figure 7. Customer Evaluation Board Table 5. Evaluation Boards Configuration Options
Component R1, R2, R7, C2, C4, C5, C6, C12, C13, C14, C15 R3, R4, R15, R16 Function Supply Decoupling. Power supply decoupling resistors and filter capacitors. Default Conditions R1, R2, R7 = 0 (Size 0603) C4, C6, C13, C14 = 100 pF (Size 0603) C2, C5, C12, C15 = 0.1 F (Size 0603) R3=R4=R16=open R15=0 (Size 0402) R6 = 1.82 k (Size 0603) C11 = 100 pF (Size 0603) C3 = 1000 pF (Size 0402) R14 = 100 (Size 0603) C16 = open (Size 0603) L1 = 0 (Size 0603) C1 = 1000 pF (Size 0402) C8 = 100 pF (Size 0402) C7 = 100 pF (Size 0402) R8 = 10 k (Size 0603) R9 = 0 (Size 0603) T1 = TC2-1T, 2:1 (Mini-Circuits) R10=R11 = 0 (Size 0603) R12 = 100 (Size 0603) Z1 = Z2 = Open Z3 = Z4 = Open
R6, C11 C3, R14, C16, L1
Jumpers for IF output interface. The eval board can be configured to provide a balanced differential output by removing R15 and T1 and adding 0- resistors for R3, R4, and R16 and adding suitable choke inductors for Z1 and Z3. RBIAS resistor that sets the bias current for the mixer core. The capacitor provides ac bypass for R6. RF Input. C3 Provides dc block for RF input. R14 provides a resistive input termination. C16 and L1 are provided for reactive matching the input.
C1 C8 C7 SW1 R8, R9 T1, R10, R11, R12, Z1, Z2, Z3, Z4
RF Common AC Coupling. Provides dc block for RF input common connection. LO Input AC Coupling. Provides dc block for the LO input. LO Common AC Coupling. Provides dc block for LO input common connection. Power Down. The part is on when the PWDN is connected to a low potential. The part is disabled when PWDN is connected to the positive supply via SW1. R8 provides a pull-down when SW1 is open and can be used as a termination when excercising the PWDN feature with an external generator. IF Output Interface. R12 Provides a real 100 - termination to the open collector outputs. T1 converts differential, high impedance IF output to single-ended. The center tap of the primary is used to supply the bias voltage (VS) to the IF output pins.
Rev. PrB | Page 7 of 8
AD8342 OUTLINE DIMENSIONS
0.50 0.40 0.30
Preliminary Datasheet
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
0.60 MAX
PIN 1 INDICATOR
16 1
13 12
BOTTOM VIEW
1.65 1.50 SQ* 1.35
9
8
5
4
0.25 MIN
1.50 REF
* COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 7. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body (CP-16-3) Dimensions in millimeters
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR05352-0-1/05(PrB)
Rev. PrB | Page 8 of 8
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